1. Field of the Invention
The present invention relates to a gate driving circuit and a display apparatus having the gate driving circuit. More particularly, the present invention relates to a gate driving circuit capable of improving output characteristics thereof and a display apparatus having the gate driving circuit.
2. Discussion of the Background
In general, a liquid crystal display (LCD) device includes an LCD panel having a lower substrate, an upper substrate connected to and facing the lower substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate in order to display an image.
The LCD panel includes a plurality of gate lines, a plurality of data lines and a plurality of pixels. Each pixel may be connected to a gate line and a data line. More specifically, a control electrode or gate electrode of a pixel thin film transistor may be connected to a gate line, and an input electrode of the pixel thin film transistor may be connected to the data line. A gate driving circuit can be directly formed on the LCD panel through a thin film forming process. The gate driving circuit may be connected to each gate line, and may sequentially output a gate signal to each gate line.
Generally, a gate driving circuit includes a shift register in which stages are connected in series. Each stage may include driving transistors arranged to apply a gate signal, such as a voltage signal with a level corresponding to a turn-on voltage or a turn-off voltage, to a corresponding gate line of the gate lines. Specifically, each stage may include a pull-up transistor connected to a gate line to output a gate signal, and a carry transistor connected to an input terminal of a next stage in the series of stages to output a carry signal used to control the driving of the next stage. Therefore, because separate transistors output the gate signal and the carry signal, the gate driving circuit may prevent a distorted signal caused by a load connected to the gate line from being applied to the next stage.
However, in a conventional gate driving circuit, a control terminal of the pull-up transistor and a control terminal of the carry transistor are commonly connected to a node, referred to as the Q-node, in a stage. Further, the Q-node should be maintained at an electric potential corresponding to a turn-off voltage lower than a threshold voltage of the pull-up transistor and the carry transistor during a (n−1)H period, which is after a 1H period, where a gate signal and a carry signal have a low level. The Q-node may then be maintained at an electric potential corresponding to a turn-on voltage that is higher than the threshold voltage of the pull-up transistor and the carry transistor during a 1H period when the gate signal and the carry signal have a high level.
However, in a conventional structure, a ripple phenomenon may occur at the Q-node during the (n−1)H period. More specifically, because of a first clock signal and a second clock signal applied to the gate driving circuit, the electric potential at the Q-node may not remain constant but, rather, may vary or ripple. When the electric potential at the Q-node ripples, the electric potential may exceed a threshold voltage of the pull-up transistor and the carry transistor, and as a result the pull-up transistor and the carry transistor may not remain off during the (n−1)H period. Consequently, a level of the gate signal and a level of the carry signal may also ripple.